How DSP is Enabling 224 Gbps Serial Links

Alphawave IP CEO Tony Pialis recently gave a presentation about how DSP is enabling 224 Gbps serial links at the Design & Reuse virtual IP-SOC event. Below we outline some of the highlights and information from this presentation.

DSP SerDes Introduction

Tony started by discussing the differences between an analog SerDes and a digital, or DSP SerDes. He explained that an analog SerDes can work reliably up to 36db NRZ or 30db PAM4. Since all equalization is implemented in the continuous time domain, this technology is sensitive to process variation. With a DSP-based design, most of the equalization is done digitally, allowing for more robust operation to 45db NRZ and 36db+ PAM4. This kind of design is also not very sensitive to process variation. Tony pointed out that the high-speed ADC required for a digital design like this is challenging to build.

Tony then went into some detail about analog linear equalization vs. DSP linear equalization. Clearly, the DSP approach is a better match for the demands of high-speed links.

The Road to 200Gbps Serial Links

Next, Tony discussed the challenges of getting from current 112Gbps PAM4 SerDes to 224Gbps PAM4 devices. Keeping the architecture the same, one can see that the reach for the device is dramatically reduced – roughly one inch vs. one foot. This is a serious challenge. The data is summarized in the figure below.

Scaling Symbol Rates to 224Gbps
Scaling Symbol Rates to 224Gbps

Given that package and board material aren’t likely to change much in the next couple of years, a new approach to increase data throughput for existing channels is needed. One that doesn’t suffer from the tradeoff issues shown above. Tony examined several alternative modulation schemes. Each has its own strengths and weaknesses relative to required channel bandwidth and signal-to-noise (SNR) ratio. He focused on PAM8 as a good candidate given its low channel bandwidth requirements. The various modulation techniques and their requirements are summarized in the figure below.

High Capacity Modulation Schemes
High Capacity Modulation Schemes

The next challenge to tackle is how to manage the SNR degradation of PAM8. One step toward a solution is to use a “maximum likelihood sequence detector.”  This advanced DSP detector uses an approach called Viterbi Detection to make data slicing decisions based on a sequence of data vs. on a single symbol which is the typical approach. This minimizes error across a sequence of symbols and results in an improvement in SNR of about 1-3 db.

Next, Tony focused on forward error correction (FEC). Using new, third-generation soft FECs based on approaches such as block turbo codes, one can recover over 10 db of bit error rate, thus compensating for the challenges of PAM8 further.


Tony concluded with an overview of Alphawave’s world-leading portfolio of DSP-based PHYs covering many protocols and applications, short and long reach. The portfolio is available and silicon-proven on TSMC 7nm and 5nm processes. With this technology platform, Tony sees a path to 224Gbps. If you’d like to learn more about Alphawave IP’s assessment of the future and how its technology fits, you can see Tony’s complete D&R presentation by registering here.

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